Synopsys will build an AI model that acts as an expert in semiconductor design, and this will be done in collaboration with OpenAI.
The company announced the project during its Investor Day, reinforcing its pledge to move “from standardized IP to dedicated IP.” As a showcase, the initiative will feature a new contract worth “more than a billion dollars” with Amazon.
The model itself will be named GPT-Synopsys. Details remain scarce for the moment, aside from the fact that it “will run on infrastructure hosted by OpenAI” and will leverage Synopsys’ EDA tooling.
OpenAI has already found footholds at Synopsys
OpenAI’s LLMs already have established footholds within Synopsys. They served as the initial substrate for the Synopsys.ai Copilot offering. Launched in 2023, this suite today comprises five assistance modules (script creation, test benches, RTL code generation, linting, and general-purpose help) built on a mix of commercial and open-source LLMs, complemented by prompts and proprietary RAG pipelines.
Ansys – a competitor that Synopsys acquired last year for more than €30 billion – also has its own generative layer powered by OpenAI. It is embodied in the Engineering Copilot assistant, focused on technical support.
The transition to an agent-based approach is branded under the Autopilot Platform. The promise is to deliver families of specialized agents for the different segments of EDA, while preserving the choice of compute and LLMs.
“Nine months from idea to tape-out”: Jalapeño, a milestone reached
OpenAI has already leveraged its AI models for its own semiconductor design needs. The standout achievement goes by the name Jalapeño. This inference chip, designed in collaboration with Broadcom, drew considerable attention precisely because it went from the initial concept to tape-out in just nine months.
Cédric Gouy-Pailler leads the artificial intelligence research program at CEA-List. Speaking at the latest Big Data & AI Paris show on components and systems for digital infrastructures, he did not miss Jalapeño and confirmed that “we are witnessing the massive introduction of AI into the chip-design process.”
Drawing on data from Microsoft, Gouy-Pailler stressed that it appears possible, within a horizon of a few months to a few years, to reduce energy consumption per inference by a factor of 8 to 20. Gains of 3 to 4x on the model itself, 2 to 3x on deployment optimization, and 1.5 to 2x on hardware could be achieved.
For further context, a synthesis of measures proposed by the European Commission under Chips Act 2.0 is worth reviewing. It maintains the objective of establishing a cloud platform for semiconductor design. When the text was proposed (June 2026), the hosting provider had already been chosen, and negotiations were underway with EDA tool vendors. Brussels expected to conclude these by autumn, aiming for an operational phase before 2027.
