No more TDP—call it “default CPU power.”
With its 6th generation EPYC chips (“Venice”), AMD has shifted to this new indicator, which reflects the cumulative consumption of compute plus I/O for a given performance target.
Up to 256 cores with EPYC Venice
Venice CPUs use Zen 6 and 6c cores. They are split into four families.
At the top end, the EPYC 9006 SP7 (9 SKUs) range from 64 to 256 physical cores, for 300 to 600 W of default power. They are expected in Q4 2026.
Scheduled for H1 2027, the EPYC 9006 SP8 (22 SKUs) are aimed at more compact environments, with 8 to 128 physical cores and 130 to 400 W of default power.
The 9006X SP7 series targets HPC, with more L2 cache than the 9006 SP7 and a maximum frequency raised to 5.15 GHz. As for the 9006 LP (low power; formerly Verano), they target the leading nodes within agentic architectures.
A GPU Instinct at the intersection of AI and HPC
Launched in parallel with EPYC Venice, the MI400 Instinct GPU lineup currently comprises two models.
On one side, the MI455X, equipped with 432 GB of HBM4 (23.3 TB/s theoretical bandwidth) and announced at 20 PFLOPS in FP8 (sparse). As is often the case with these chips, AMD did not officially disclose a TDP (the Vera Rubin reference hovers around 2000 W).
On the other hand, the MI430X, endowed with the same amount of DRAM, but positioned for the AI/HPC convergence, with a theoretical FP64 performance of 288 TFLOPS. Availability expected in 2027, with AI (gigafactories) in sight. The Alice Recoque supercomputer will carry it.
Helios AI or the promise of exaflop racks for FP8 inference
The EPYC Venice CPUs and the MI455X Instinct GPUs are—the Pensando DPU/NIC aside—the building blocks of Helios AI racks. On the menu, up to 72 GPUs, 18 CPUs and 31 TB of HBM4 memory (1.7 PB/s). Theoretical peak power: 1.4 exaflops in FP8 (a numeric format often used in production for inference).
Helios AI racks use the new ORW (Open Rack Wide) standard from the Open Compute Project. Shipments are expected to begin this quarter. Bull, HPE, Lenovo and Supermicro, among others, will supply systems.
Ryzen AI Embedded: from P100 to X100, with a doubled TDP
For robotics and more broadly “physical” AI, AMD is rolling out the Kria AI boards. They rely on the latest generation of Ryzen AI Embedded processors (X100).
These combine a CPU (8 to 16 Zen 5 cores), an iGPU (32 or 40 compute units) and an NPU (50 TOPS), for a TDP of 55 W (compared with 28 W for most P100s). Maximum unified memory capacity: 128 GB (273 GB/s on LPDDR5X-8533 with a 256-bit bus).
Mass production of Kria AI boards is expected in Q4 2026, with partners including Arbor, Congatec, iBase, IEI, Sapphire and Seavo.
AMD plans a joint solution with Cerebras for this year
At the same time, OpenAI plans to deploy Helios AI racks. This will be the first phase of the 6 GW rollout announced in October 2025.
Latest word has it that Meta has begun testing these same racks and validating the EPYC Venice.
AMD is also working with Cerebras. It commits to unifying its chips with the Helios AI racks into a “disaggregated inference system.” A joint solution is expected to emerge by the end of 2026, initially within the Cerebras Cloud offering.
Further reading:
The AI data center, the ideal blueprint for Arm’s first CPU
After DRAM, the specter of a CPU shortage
Will Meta become a neocloud?
IaaS, inference, desktop workloads… Microsoft makes its cloud a little more “local”
From AWS to GCP, how Slack’s AI became multi-cloud
